DFM Tips & Tricks II

- Clear identification of board layers-

Even a single sided a board can be viewed from above or below. Clearly marking all layers with right reading text will enable the board manufacturer to verify the proper orientation for your board. The more layers that are employed to make a board, the more important this becomes.

- Lack of accompanying documentation-

This is something that should be included with all work orders. The variables that go into making a printed circuit board include - the number of layers, quantity, size, board finish, overall and plating thickness' and delivery time. Multilayer circuit boards also require information as to layer placement and the thickness of the dielectric between layers. Any other information specific to your files should be sent along with your jobs to ensure that your specifications are met.

- Not identifying the critical impedance controlled tracks on a layer by layer basis-

Not identifying those tracks of particular concern can lead to yield losses that are unusually high, due to the assumption that all layers require critical impedance control. Designers should specify all critical tracks on each layer with a seperate aperture (D) code to enable accurate quality assessment and track width manipulation to accomodate etch factors and core thickness variations.

- Improper selection of a datum point-

The lower left corner of a board or the corner of an etched feature is often designated as datum point 0,0. Etched features are subject to dimensional variations. Tolerance allowances for overall board dimensions make the corner of the board a less than perfect choice for the datum point. The best solution is to designate the centre of a hole as being 0,0.

- Too many different hole sizes - often only a few mils apart-

This increases costs due to the many tool changes while drilling. One solution is that wherever possible group close hole sizes together (ie make all .033,.034,.035 holes .034 as the others will still pass tolerance requirements.

- Stipulating a minus tolerance on via holes

This might cause limitations on panel size due to pad/hole ratios. High current densities might plate the hole down. Reworking the vias to unplug the holes is time consuming.

Specify if vias can be filled or designate tolerances as a "+" allowance only or specify that vias may be plugged or filled.

- Ground planes

whenever possible, ground planes ( and traces) should end approx 0.010" from the edges of the board to ensure against accidental shorting with metal chassis and cases.

- Removing nonfunctional pads on inner layers and routing traces too close to plated through holes.

In designing a board minimum spacing is an important consideration. Often, this spacing does not take into account manufacturing tolerance buildup ( ie maximum allowable misregistration combined with maximum etchback). A trace routed between plated through holes on a layer with the nonfunctional pads removed can actually short out during an electrical test resulting in a scrapped unit.

If pads do have to be removed (as is the case in flex or rigid/flex boards it is advisable to let the manufacturer take care of this.

- Exposed traces.

Traces are too close or actually pass through solder mask openings. Also specifying solder masks that are outdated for SMT applications.

Exposed traces will lead to solder shorts,low yields. To avoid these problems, redesign layouts to incorporate smaller solder mask openings and specify a mask type ( such as S222) that can keep within required tolerances.

- Uneven distribution of copper. Extensive ground planes in one area of a board and isolated traces in another.

These circumstances can cause uneven plating and etching, burning, funnelling in through holes and excess warpage. Ground planes can be completed in a cross hatched pattern and added to areas around isolated traces to provide for a more uniform distribution of copper.

Surface Mount Problems

- Placing vias under components

Once thought to be a neat and orderly manner in which to layout SMT boards - vias placed under components create problems after assembly as the flux used in assembly can cause corrosion in the via leading to overall board failure.

- Traces that are too small

Designers have specified trace widths that appear to be compatible with the components, where they actually need to use traces that are the same size as those on a non SMT board.

Other Points

Steadily the allowable production tolerances in circuit board fabrication are decreasing. Along with the need for tighter registration comes the question of allowable process techniques. Both of these elements in board manufacture contribute to lower and lower yields from both prototype and production runs. Reducing trace widths from .010" to.008" can make the difference between a board that can be consistently produced and a board that could fail in manufacturing.

Trimming pads to allow for the routing of a trace is a common practise that can lead to unreliable soldering. Manufacturability and reliability can be enhanced by the use of teardrop shaped joins between pads and traces.

The physical constraints of reliable manufacturing such as minimum feature size and spacing, the use of blind or buried vias and the number of layers need to be adhered to as well as the engineering rules relating to crosstalk and pin ordering.

In routing, traces should be distributed evenly across the design, vias should be kept to a necessary minimum, traces thickened where possible and potential acid traps smoothed out. Consider the problem of test points for SMT designs at the planning stage and develop test strategies for designs where access is restricted.