Controlling Signal Timing

Standard reference sources (Motorola's MECL System Design Handbook, for example1.7.1) give several formulas that relate to the propagation delay of a signal along a trace on a circuit board. These formulas have been combined and summarized in Figure 1.7a. The first part of the formula provides the basic propagation time under unloaded conditions. In that formula, a = 1 and b = 0 for Stripline configurations and a = .475 and b = .67 for Microstrip.
Formula For Propagation Delay Along a Trace

The second part of the formula provides for the slowing of signals due to the capacitive loading along the line. This capacitive loading is caused by the circuit loads on the line and stray, parasitic capacitances.

People tend to use 2 nsec/ft. as a standard rule of thumb for propagation delay when designing circuits. But in fact this figure might be off by as much as 50%, depending on design specifics.

The first important variable in this equation is Er the relative dielectric coefficient. People often use a value of 4.2 for standard FR-4 board material. Actual values can easily range from 4.0 to 4.4 (or more) in the real world, and Er even varies within a layer as a result of temperature and pressure effects during fabrication. This range results in an uncertainty of Tpd of approximately 5%, or about .1 nsec/ft. That's 8.3 Psec/in., or 100 Psec in a 12 inch line.

The second important factor is Cd, the sum of the capacitance effects of the loads on the line. A fanout of 8 loads of about 5pf each on a 12 inch line can slow Tpd by as much as 50% (1 nsec/ft. or 83 Psec/in). The calculation of the exact amount requires a calculation of Co, which itself depends on Er and the board interlayer geometries.

The bottom line is that before the delay along a line can be adjusted accurately to meet circuit needs, the actual Tpd along the line must be known. The actual Tpd along the line depends, among other things, on the design the PCB designer is going to create (i.e. the path lengths) and the processes the board fabricator is going to use.

As board designers, UltraCAD can trim a line length as close as one mil. This is within a fraction of a Psec. Since, in practice, the uncertainty of Tpd is as much as 80 Psec in an inch, design tolerances can be almost two orders of magnitude tighter than other sources of uncertainty!

So what does the circuit design engineer do? First, understand the limitations of accurately estimating Tpd before we begin to adjust signal delay times by adjusting line lengths. Then, allow us to work closely with you and the board house who will fabricate the boards. We have found that only a small fraction of board houses really understand these concepts and their processes well enough to help their customers meet very tight requirements. If yours can't, we can help you select one. The cost will not be any higher (neither we nor the board houses charge for such cooperation _ in fact we all enjoy working with customers who design their circuits so carefully), but be sure to allow extra project time to do it right!

Limits on adjustments:

There is a lower limit on propagation time. It's hard to make a trace shorter than the straight line connecting two points! But you can add time to a trace by increasing its length. Conceptually, there is no limit to how much time you can add (up to available surface area!).

UltraCAD can adjust an individual line (or match a differential pair of lines) as close as one mil (.001) without much difficulty. That's about .2 Psec. Although we can adjust lengths even tighter than this, the benefits are seldom worth the effort.

The above article was written by the staff at UltraCad Design in Bellevue, WA.
They can be reached at (206)450 9708

© 2000 Omni Graphics Ltd.